Neuromorphic electronics: a beginning guide

‘Neural network (NN)’ is one of the new buzz words, but ‘neuromorphic’ is barely known outside of geeky community. It means ‘to mimic biological architectures in the nervous system’. As is well-known, the nervous system is in extreme complexity; mimicking the whole architecture is impossible. Thus, the essential point is abstraction.The biological neuron, an electrically excitable cell that communicates with
each other, can be replaced by a nonlinear device (artificial neuron) with a threshold for logic functions. The biological synapse, a joint between two neurons, with neuroplasticity can be a memory device (artificial synapse). The artificial neurons and synapses lead to the formation of artificial NN (ANN), and the architecture of ANN is crucial. Ideally, the properties of the artificial neuron and synapse should
determine the architecture of ANN. If the artificial neuron can mimic ‘leaky-integrate and fire (LIF)’ property, and the artificial synapse can mimic ‘spike-time-dependent plasticity (STDP)’ property of the biological counterparts, a spiking neural network (SNN) is plausible. However, in the present research, algorithm plays the leading role to determine both the architecture and devices, though the biological nervous system does not have any algorithms at all. An interesting example is the deep-learning (DL) algorithm for multi-layer NN. Because of its remarkable success in highly efficient statistical processing (e.g., image recognition), development of DL algorithm and computer chip for multi-layer NN (i.e., DL accelerator) are believed to realise artificial intelligence. However, the brain does not work with any algorithms. Our brain consumes only 20W, while DL requires immense power (Alpha Go, which defeated world champion, needed 200 kW), because the algorithm requires huge logic calculations.
In this talk, I would like to give an introduction of the abstraction for preparing the neuromorphic devices and architectures. I would also like to discuss on how to escape from the kingdom of the DL algorithm for real brain-like low-power computation.

Short Biography
Dr Isao H. Inoue received BSc, MSc, and DSc degrees in Physics from the University of Tokyo in 1990, 1992 and 1999, respectively. He became a researcher with tenure at the Electrotechnical Laboratory (ETL) in 1992 and a senior researcher in 1999. From 1999 to
2001, Dr Inoue was a visiting scholar at Cavendish Laboratory, University of Cambridge. In 2001, the Japanese government reorganised ETL with several other national institutes to found the National Institute of Advanced Industrial Science and Technology (AIST). Since then, he has been a senior researcher of AIST trying to work on missing links between the fundamental physics and the emerging electronics: e.g., quantum critical phenomena and neuromorphic electronic devices.

isaocaius@gmail.com; https://sites.google.com/view/isao/