Error protected gates en route to scalable quantum computing

Scalable quantum computing is a goal pursued by many companies and research groups around the world, as it holds promise to revolutionize computing and communications. In Quantum Transistors we aim to build a solid state quantum processor. We follow a hybrid approach, combining optically addressable spin defects in diamond and silicon-based photonic integrated circuits. In this talk I'll first present our general approach toward scalability. I'll then focus on one of the ingredients, namely, error protected spin-spin grates. I'll present the problem, the known solutions, and our latest results, showing over an order of magnitude reduction in the error per gate.